Usbfifo Clear Register 0 (Ufclr0) - Hitachi H8S/2215 Series Hardware Manual

15.3.7

USBFIFO Clear Register 0 (UFCLR0)

UFCLR0 is a one-shot register used to clear the FIFO for each end point from EP0 to EP3. Writing
1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in UFCLR0
clears the data for which the corresponding PKTE bit in UTRG0 is cleared to 0 after data write, or
data that is validated by setting the corresponding PKTE bit in UTRG0. For OUT FIFO, writing 1
to a bit in UFCLR0 clears data that has not been fixed during reception or received data for which
the corresponding RDFN bit is not set to 1. Accordingly, care must be taken not to clear data that
is currently being received or transmitted. EP2i, EP2o, EP3i, and EP3o FIFOs, having a dual FIFO
configuration, are cleared by entire FIFOs. Note that this trigger does not clear the corresponding
interrupt flag.
Bit Bit Name Initial Value R/W
7 EP3oCLR 0
6 EP3iCLR 0
5 EP2oCLR 0
4 EP2iCLR 0
3 EP1iCLR 0
2 EP0oCLR 0
1 EP0iCLR 0
0 — 0
Description
W EP3o clear
0: Performs no operation.
1: Clears EP3o OUT FIFO.
W EP3i clear
0: Performs no operation.
1: Clears EP3i IN FIFO.
W EP2o clear
0: Performs no operation.
1: Clears EP2o OUT FIFO.
W EP2i clear
0: Performs no operation.
1: Clears EP2i IN FIFO.
W EP1i clear
0: Performs no operation.
1: Clears EP1i IN FIFO.
W EP0o clear
0: Performs no operation.
1: Clears EP0o OUT FIFO.
W EP0i clear
0: Performs no operation.
1: Clears EP0i IN FIFO.
R Reserved
This bit is always read as 0 and cannot be modified.
Rev. 3.0, 10/02, page 453 of 686