Duty Adjustment Circuit; Medium-Speed Clock Divider; Bus Master Clock Selection Circuit; Figure 21.5 External Clock Input Timing - Hitachi H8S/2215 Series Hardware Manual

EXTAL
The external clock input conditions when the duty adjustment circuit is not used are shown in table
21.4. When the duty adjustment circuit is not used, note that the maximum operating frequency
depends on the external clock input waveform. For example, if t
= 6.25 ns, the maximum operating frequency becomes 13.3 MHz depending on the clcok cycle
time of 75 ns.

Table 21.4 External Clock Input Conditions when Duty Adjustment Circuit is not Used

Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
21.3

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (ø).
21.4

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.
21.5

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed clocks (ø/2, ø/4, ø/8, ø/16, ø/32).
t
EXH
t
EXr

Figure 21.5 External Clock Input Timing

Symbol Min
t 31.25
EXL
t 31.25
EXH
t —
EXr
t —
EXf
t
EXL
V
CC
t
EXf
= T = 31.25ns and t
EXL EXH
Max Unit
— ns
— ns
6.25 ns
6.25 ns
Rev. 3.0, 10/02, page 601 of 686
0.5
= t
EXr EXf
Test Conditions
Figure 21.5