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24.4.3
Bus Timing
Table 24.6 shows, Bus Timing.
Table 24.6 Bus Timing
Conditions: V
= PLL V
CC
Dr V
=AV
SS
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Item
Address delay time
Address setup time
Address hold time
CS delay time
AS delay time
RD delay time 1
RD delay time 2
Read data setup time
Read data hold time
Read data access time 2
Read data access time 3
Read data access time 4
Read data access time 5
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time
Write data hold time
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus-floating time
Rev. 3.0, 10/02, page 658 of 686
=Dr V
=2.7 V to 3.6 V, Vref=2.7 V to AV
CC
CC
= 0 V, φ =13 MHz to 16 MHz,
SS
Symbol
Min
t
—
AD
0.5 × t
t
– 30
AS
cyc
0.5 × t
t
– 15
AH
cyc
t
—
CSD
t
—
ASD
t
—
RSD1
t
—
RSD2
t
30
RDS
t
0
RDH
t
—
ACC2
t
—
ACC3
t
—
ACC4
t
—
ACC5
t
—
WRD1
t
—
WRD2
1.0 × t
t
– 30
WSW1
cyc
1.5 × t
t
– 30
WSW2
cyc
t
—
WDD
0.5 × t
t
– 30
WDS
cyc
0.5 × t
t
– 15
WDH
cyc
t
50
WTS
t
10
WTH
t
50
BRQS
t
—
BACD
t
—
BZD
CC
= –40°C to +85°C (wide-range
a
Max
Unit
50
ns
—
ns
—
ns
50
ns
50
ns
50
ns
50
ns
—
ns
—
ns
1.5 × t
– 65
ns
cyc
2.0 × t
– 65
ns
cyc
2.5 × t
– 65
ns
cyc
3.0 × t
– 65
ns
cyc
50
ns
50
ns
—
ns
—
ns
70
ns
—
ns
—
ns
—
ns
—
ns
—
ns
50
ns
80
ns
, V
= PLLAV
=
SS
SS
Test Conditions
Figures 24.7, 24.8, 24.10
Figures 24.7, 24.8
Figures 24.7, 24.8, 24.10
Figures 24.7, 24.8
Figures 24.7, 24.8, 24.10
Figures 24.7, 24.8, 24.10
Figures 24.7, 24.8, 24.10
Figure 24.7
Figures 24.7, 24.10
Figure 24.8
Figure 24.8
Figure 24.8
Figures 24.7, 24.8
Figure 24.7
Figure 24.8
Figures 24.7, 24.8
Figure 24.8
Figure 24.8
Figure 24.9
Figure 24.9
Figure 24.11
Figure 24.11
Figure 24.11
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