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Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
Set data transfer format in
SMR and SCMR
Set value in BRR
1-bit interval elapsed?
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
<Initialization completion>
13.4.5
Data Transmission (Asynchronous Mode)
Figure 13.9 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
Wait
No
Yes
Figure 13.8 Sample SCI Initialization Flowchart
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
[1]
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[2]
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
[3]
an external clock or average
transfer rate clock by ACS2 to
ACS0 is used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
[4]
Rev. 3.0, 10/02, page 385 of 686
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