Operation; Figure 8.5 Flowchart Of Dtc Operation - Hitachi H8S/2215 Series Hardware Manual

8.5

Operation

Register information is stored in an on-chip memory. When activated, the DTC reads register
information in an on-chip memory and transfers data. After the data transfer, it writes updated
register information back to the memory. Pre-storage of register information in the memory makes
it possible to transfer data over any required number of channels. The transfer mode can be
specified as normal, repeat, and block transfer mode. Setting the CHNE bit to 1 makes it possible
to perform a number of transfers with a single activation source (chain transfer).
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Table 8.3 summarizes DTC functions.
Start
Read DTC vector
Register information read
Data transfer
Write register information
CHNE = 1
No
Transfer
counter = 0
or DISEL = 1
No
Clear an active flag
End

Figure 8.5 Flowchart of DTC Operation

Next transfer
Yes
Yes
Clear DTCER
Interrupt exception
handling
Rev. 3.0, 10/02, page 205 of 686