Interrupt Sources; Table 15.5 Sci Interrupt Sources - Hitachi H8S/2215 Series Hardware Manual

15.4

Interrupt Sources

This module has three interrupt signals. Table 15.5 shows the interrupt sources and their
corresponding interrupt request signals. EXIRQ interrupt signals are activated at low level. The
EXIRQ interrupt requests can only be detected at low level (specified as level sensitive). The
suspend/resume interrupt request IRQ6 must be specified to be detected at the falling edge
(falling-edge sensitive) by the interrupt controller register.

Table 15.5 SCI Interrupt Sources

Transfer
Register Bit Mode
UIFR0 0
Control transfer
(EP0)
1
2
3
4 Interrupt_in transfer
(EP1i)
5
6 —
7 Status
UIFR1 0 Bulk_in transfer
(EP2i)
1
2 Bulk_out transfer
(EP2o)
3 —
4 Isochronous_in
Transfer (EP3i)
5
6 Isochronous_out
Transfer (EP3o)
7
UIFR2 0 Bulk_in transfer
(EP4i)
1
Rev. 3.0, 10/02, page 482 of 686
Interrupt
Source Description
1
SetupTS*
Setup command
receive completion
1
EP0iTS* EP0i transfer
completion
1
EP0iTR* EP0i transfer request
1
EP0oTS * EP0o receive request
EP1iTS EP1i transfer
completion
EP1iTR EP1i transfer request
Reserved —
BRST Bus reset
EP2iEMPTY EP2i FIFO empty
EP2iTR EP2i transfer request
EP2oREADY EP2o data ready
Reserved —
EP3iTR EP3i transfer request
EP3iTF EP3i abnormal
transfer
EP3oTS EP3o normal receive
EP3oTF EP3o abnormal
receive
EP4iEMPTY EP4i FIFO empty
EP4iTR EP4i transfer request
Interrupt
Request DMAC
Signal Activation
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
— —
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or DREQ0 or
EXIRQ1 DREQ1*
2
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or DREQ0 or
EXIRQ1 DREQ1*
3
— —
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
X X
X X
EXIRQ0 or DREQ0 or
EXIRQ1 DREQ1*
4
EXIRQ0 or
X
EXIRQ1