Hitachi H8S/2215 Series Hardware Manual page 37

12.3.1 Watchdog Timer Mode ........................................................................................ 351
12.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 352
12.3.3 Interval Timer Mode............................................................................................ 353
12.3.4 Timing of Setting of Overflow Flag (OVF)......................................................... 353
12.4 Interrupts........................................................................................................................... 354
12.5 Usage Notes ...................................................................................................................... 354
12.5.1 Notes on Register Access..................................................................................... 354
12.5.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 355
12.5.3 Changing Value of CKS2 to CKS0...................................................................... 356
12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 356
12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 356
Section 13 Serial Communication Interface ......................................................357
13.1 Features............................................................................................................................. 357
13.1.1 Block Diagram..................................................................................................... 358
13.2 Input/Output Pins .............................................................................................................. 361
13.3 Register Descriptions ........................................................................................................ 361
13.3.1 Receive Shift Register (RSR) .............................................................................. 361
13.3.2 Receive Data Register (RDR) .............................................................................. 362
13.3.3 Transmit Data Register (TDR)............................................................................. 362
13.3.4 Transmit Shift Register (TSR) ............................................................................. 362
13.3.5 Serial Mode Register (SMR)................................................................................ 363
13.3.6 Serial Control Register (SCR).............................................................................. 365
13.3.7 Serial Status Register (SSR) ................................................................................ 367
13.3.8 Smart Card Mode Register (SCMR) .................................................................... 370
13.3.9 Serial Extended Mode Register 0 (SEMR_0) ...................................................... 371
13.3.10 Bit Rate Register (BRR) ...................................................................................... 375
13.4 Operation in Asynchronous Mode .................................................................................... 381
13.4.1 Data Transfer Format........................................................................................... 381
13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 383
13.4.3 Clock.................................................................................................................... 384
13.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 384
13.4.5 Data Transmission (Asynchronous Mode)........................................................... 385
13.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 388
13.5 Multiprocessor Communication Function......................................................................... 391
13.5.1 Multiprocessor Serial Data Transmission ............................................................ 392
13.5.2 Multiprocessor Serial Data Reception ................................................................. 394
13.6 Operation in Clocked Synchronous Mode ........................................................................ 396
13.6.1 Clock.................................................................................................................... 397
13.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 397
13.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 398
13.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 400
13.6.5 Simultaneous Serial Data Transmission and Reception
Rev. 3.0, 10/02, page xxxvii of lviii