Table of Contents
Advertisement
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR
ABWn
ASTn
0
0
1
1
0
1
6.4.3
Bus Interface for Each Area
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (see section 6.6, Basic Bus Interface and section
6.7, Burst ROM Interface) should be referred to for further details.
(1) Area 0: Area 0 includes on-chip ROM, and in ROM-disabled extended mode, all of area 0 is
external space. In ROM-enabled extended mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
(2) Areas 1 to 6: In external extended mode, all of areas 1 to 6 are external spaces. When areas 1
to 6 external space are accessed, the CS1 to CS6 pin signals respectively can be output. Only
the basic bus interface can be used for areas 1 to 6. Area 6 is only for the on-chip USB. For
details, see section 15, Universal Serial Bus Interface (USB).
(3) Area 7: Area 7 includes the on-chip RAM and internal l/O registers. In external extended
mode, the space excluding the on-chip RAM and internal l/O registers, is external space. The
on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to
1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding
space becomes external space.
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7.
Rev. 3.0, 10/02, page 112 of 686
WCRH, WCRL
Bus Specifications (Basic Bus Interface)
Wn1
Wn0
Bus Width Number of Access
16
0
0
1
1
0
1
8
0
0
1
1
0
1
States
2
3
2
3
Number of Program
Wait States
0
0
1
2
3
0
0
1
2
3
Advertisement
Table of Contents
