Figure 6.25 Bus-Released State Transition Timing - Hitachi H8S/2215 Series Hardware Manual

Figure 6.25 shows the timing for transition to the bus-released state.
Address bus
Data bus
,
[1] Low level of
[2]
master.
[3]
[4] High level of
[5]
Note : n = 0 to 7
CPU cycle
T T T
0 1 2
Address
Minimum
1 state
[1]
pin is sampled at rise of T
pin is driven low at end of CPU read cycle, releasing bus to external bus
pin state is still sampled in external bus released state.
pin is sampled.
pin is driven high, ending bus release cycle.

Figure 6.25 Bus-Released State Transition Timing

External bus released state
[2] [3]
state.
2
CPU
cycle
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[4] [5]
Rev. 3.0, 10/02, page 137 of 686