Usbfifo Clear Register 1 (Ufclr1) - Hitachi H8S/2215 Series Hardware Manual

15.3.8

USBFIFO Clear Register 1 (UFCLR1)

UFCLR1 is a one-shot register used to clear the FIFO for each endpoint from EP4 to EP5. Writing
1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in UFCLR1
clears the data for which the corresponding PKTE bit in UTRG1 is cleared to 0 after data write, or
data that is validated by setting the corresponding PKTE bit in UTRG1. For OUT FIFO, writing 1
to a bit in UFCLR1 clears data that has not been fixed during reception or received data for which
the corresponding read completion bit is not set to 1. Accordingly, care must be taken not to clear
data that is currently being received or transmitted. EP4i and EP4o FIFOs, having a dual FIFO
configuration, are cleared by entire FIFOs. Note that this trigger does not clear the corresponding
interrupt flag.
Bit Bit Name Initial Value R/W
7 to 3 — 0
2 EP5iCLR 0
1 EP4oCLR 0
0 EP4iCLR 0
Rev. 3.0, 10/02, page 454 of 686
Description
R Reserved
These bits are always read as 0 and cannot be
modified.
W EP5i clear
0: Performs no operation.
1: Clears EP5i IN FIFO.
W EP4o clear
0: Performs no operation.
1: Clears EP4o OUT FIFO.
W EP4i clear
0: Performs no operation.
1: Clears EP4i IN FIFO.