Irq Status Register (Isr) - Hitachi H8S/2215 Series Hardware Manual

5.3.4

IRQ Status Register (ISR)

ISR indicates the status of IRQ7 to IRQ0 interrupt requests. Only 0 should be written to these bits
for clearing the flag.
Bit Bit Name Initial Value R/W
7 IRQ7F 0
6 IRQ6F 0
5 IRQ5F 0
4 IRQ4F 0
3 IRQ3F 0
2 IRQ2F 0
1 IRQ1F 0
0 IRQ0F 0
Rev. 3.0, 10/02, page 82 of 686
Description
R/W [Setting conditions]
When the interrupt source selected by the ISCR
R/W
registers occurs
R/W
[Clearing conditions]
R/W
•
Cleared by reading IRQnF flag when IRQnF = 1,
R/W
then writing 0 to IRQnF flag
R/W
•
When interrupt exception handling is executed
R/W
when low-level detection is set and , IRQn input is
R/W
high
•
When IRQn interrupt exception handling is executed
when falling, rising, or both-edge detection is set
•
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0