Basic Dmac Bus Cycles; Figure 7.15 Example Of Dma Transfer Bus Timing - Hitachi H8S/2215 Series Hardware Manual

request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC
activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC.
Activation by Auto-Request: Auto-request activation is performed by register setting only, and
transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be
selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession
of the bus until the end of the transfer, and transfer is performed continuously.
7.4.8

Basic DMAC Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.15. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.
CPU cycle
φ
Address bus
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
DMAC cycle (1-word transfer)
T T T
1 2 1
Source
address

Figure 7.15 Example of DMA Transfer Bus Timing

T T T T
2 3 1 2
Destination address
CPU cycle
T
3
Rev. 3.0, 10/02, page 181 of 686