Pin Handling When 48-Mhz External Clock Is Not Needed; (On-Chip Pll Circuit Is Used); Pll Circuit For Usb; Figure 21.8 48-Mhz External Clock Input Timing - Hitachi H8S/2215 Series Hardware Manual

Table 21.5 External Clock Input Conditions when Duty Adjustment Circuit is not Used

Item
External clock frequency
(48 MHz)
Clock rise time
Clock fall time
Duty (t / t )
HIGH FREQ
EXTAL48
21.6.3 Pin Handling when 48-MHz External Clock is not Needed (On-chip PLL Circuit is
Used)
When the 48-MHz external clock is not needed, connect the EXTAL48 pin to GND (Vss) and
leave the XTAL48 pin open as shown in figure 21.9.

Figure 21.9 Pin Handling when 48-MHz External Clock is Not Used

21.7

PLL Circuit for USB

The PLL circuit has the function of tripling the 16-MHz clock from the system oscillator to
generate the 48-MHz USB operating clock. When the PLL circuit is used, set the UCKS3 to
UCKS0 bits of UCTLR. For details, refer to section 15, Universal Serial Bus (USB). When the
PLL circuit is not used, connect the PLVCC pin to VCC, and leave the PLLCAP pin open as
shown in figure 21.10.
Symbol Min
t 47.88
FREQ
t —
R48
t —
F48
t 40
DUTY
t
HIGH
90%
10%
t
R48

Figure 21.8 48-MHz External Clock Input Timing

EXTAL48
XTAL48
Max Unit
48.12 MHz
2 ns
2 ns
60 %
t
FREQ
t
LOW
t
F48
Open state
Rev. 3.0, 10/02, page 603 of 686
Test Conditions
Figure 21.8
V 0.5
CC