Interrupts; Figure 7.26 Block Diagram Of Transfer End/Transfer Break Interrupt; Table 7.10 Interrupt Source Priority Order - Hitachi H8S/2215 Series Hardware Manual

7.5

Interrupts

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.10
shows the interrupt sources and their priority order.

Table 7.10 Interrupt Source Priority Order

Interrupt Source
Interrupt
Name Short Address Mode
DEND0A Interrupt due to end of transfer
on channel 0A
DEND0B Interrupt due to end of transfer
on channel 0B
DEND1A Interrupt due to end of transfer
on channel 1A
DEND1B Interrupt due to end of transfer
on channel 1B
Enabling or disabling of each interrupt source is set by means of the DTIE bit for the
corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt
controller independently. The relative priority of transfer end interrupts on each channel is decided
by the interrupt controller, as shown in table 7.10.
Figure 7.26 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always
generated when the DTIE bit is set to 1 while DTE bit is cleared to 0.
DTE/
DTME
DTIE

Figure 7.26 Block Diagram of Transfer End/Transfer Break Interrupt

In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should
be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt
generation during setting.
Full Address Mode
Interrupt due to end of transfer
on channel 0
Interrupt due to break in transfer
on channel 0
Interrupt due to end of transfer
on channel 1
Interrupt due to break in transfer
on channel 1
Transfer end/transfer
break interrupt
Rev. 3.0, 10/02, page 191 of 686
Interrupt
Priority Order
High
Low