11.8
Usage Notes
11.8.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows this
operation.
ø
Address
Internal write signal
Counter clear signal
TCNT
Figure 11.10 Contention between TCNT Write and Clear
state of a TCNT write cycle, the clear
2
TCNT write cycle by CPU
T1
T2
TCNT address
N
H'00
Rev. 3.0, 10/02, page 341 of 686