Table of Contents
Advertisement
Write pulse application subroutine
Subroutine Write Pulse
WDT enable
Set PSU1 bit in FLMCR1
Wait (y) µs
Set P1 bit in FLMCR1
Wait (z0), (z1), or (z2) µs
Clear PSU1 bit in FLMCR1
Wait ( ) µs
Clear psu1 bit in FLMCR1
Wait ( ) µs
Disable WDT
End Sub
Note: *7 Write Pulse Width
P1 bit set time (µs)
Number of Writes n
Program
1
z0
2
z0
N1-1
z0
N1
z0
N1+1
z1
N1+2
z1
N1+3
z1
N1+N2-2
z1
N1+N2-1
z1
N1+N2
z1
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Notes:* 1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Notes:* 2 Verify data is read in 16-bit (word) units.
Notes:* 3 Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
Notes:* 4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
Notes:* 5 A write pulse of z0 or z1 is applied according to the progress of the programming operation. See Note* 7 for details of the pulse widths. When writing of additional-
programming data is executed, a z2 write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Notes:* 6 x, y, z0, z1, z2, , , , , , , and N1 are shown in section 24.8, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data
Verify Data
(D)
0
0
1
1
Rev. 3.0, 10/02, page 584 of 686
Start of programming
*
5
End of programming
Increment address
Re -program
z2
z2
z2
z2
Reprogram Data
Comments
(V)
(X)
Programming completed
0
1
1
0
Programming incomplete;
reprogram
0
1
1
1
Still in erased state; no action
Figure 19.11 Program/Program-Verify Flowchart
Start of programming
START
Set SWE1 bit in FLMCR1
Wait (x) µs
Store 128-byte program data in program
data area and reprogram data area
n = 1
m = 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Sub-Routine-Call
Apply
µs
µs
Write pulse Z0
OR Z1
Set PV1 bit in FLMCR1
Wait ( ) µs
H'FF dummy write to verify address
Wait ( ) µs
Read verify data
Write data =
verify data?
Yes
No
n ?
N1
Yes
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
Transfer reprogram data to reprogram data area
128-byte
data verification completed?
Yes
Clear PV1 bit in FLMCR1
Wait ( ) µs
No
N1 n?
Yes
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse (Additional programming)
No
m = 0 ?
Yes
Clear SWE1 bit in FLMCR1
Wait ( ) µs
End of programming
Additional-Programming Data Computation Table
Reprogram Data
Verify Data
(X')
(V)
Programming Data (Y)
0
0
0
1
1
0
1
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*
4
*
1
See Note *7 for pulse width
n
n + 1
*
2
No
m = 1
*
4
*
3
*
4
*
1
No
n
(N1 + N2)?
Yes
Clear SWE1 bit in FLMCR1
Wait ( ) µs
Programming failure
Additional-
Comments
Additional programming
0
to be executed
1
Additional programming
not to be executed
1
Additional programming
not to be executed
Additional programming
1
not to be executed
Reprogram
Advertisement
Table of Contents
