Figure 13.23 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations - Hitachi H8S/2215 Series Hardware Manual

Start transmission/reception
Read TDRE flag in SSR
No
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Clear TE and RE bits in SCR to 0
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to 0,
then set both these bits to 1 simultaneously.

Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

Rev. 3.0, 10/02, page 404 of 686
Initialization
TDRE = 1
Yes
ORER = 1
Error processing
No
RDRF = 1
Yes
All data received?
Yes
<End>
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Yes
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
[3]
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
[4]
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0.
[5]
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR and clear the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC and DMAC is activated by a
receive data full interrupt (RXI)
request and the RDR value is read.