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10.8
Usage Notes
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width. In phase counting mode, the phase difference and
overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at
least 2.5 states. Figure 10.44 shows the input clock conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes: Phase difference and overlap
Pulse width
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches the TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
φ
f = ————
(N + 1)
Where f : Counter frequency
φ : Operating frequency
N : TGR set value
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated
in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not
performed. Figure 10.42 shows the timing in this case.
Rev. 3.0, 10/02, page 320 of 686
Phase
Phase
differ-
differ-
Overlap
Overlap
ence
Pulse width
: 1.5 states or more
: 2.5 states or more
Pulse width
ence
Pulse width
Pulse width
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