A/D Control/Status Register (Adcsr); Table 16.2 Analog Input Channels And Corresponding Addr Registers - Hitachi H8S/2215 Series Hardware Manual

The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit.

Table 16.2 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel
AN0
AN1
AN2, AN14
AN3, AN15
16.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.
Rev. 3.0, 10/02, page 536 of 686
A/D Data Register to Be Stored the Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD