Usb Test Register 1 (Utstr1) - Hitachi H8S/2215 Series Hardware Manual

15.3.42 USB Test Register 1 (UTSTR1)

UTSTR1 allows internal or external transceiver input signals to be monitored. When the FADSEL
bit of UCTLR is set to 0, internal transceiver input signals can be monitored. When the FADSEL
bit is FADSEL =1, external transceiver input signals can be monitored. Table 15.4 shows the
relationship between UTSTR1 settings and pin inputs.
Bit Bit Name Initial Value R/W
7 VBUS —*
UBPM
6 —*
5 to 3 — 0
2 RCV —*
1 VP —*
0 VM —*
Note:* Indicates an undefined value.
Description
R Internal/External Transceiver Input Signal Monitor Bits
R VBUS: Monitors VBUS pin
UBPM: Monitors UBPM pin
R Reserved
These bits are always read as 0 and cannot be
modified.
R Internal/External Transceiver Input Signal Monitor Bits
R RCV: Monitors the RCV signal of the internal/external
transceiver
R
VP: Monitors the VP signal of the internal/external
transceiver
VM: Monitors the VM signal of the internal/external
transceiver
Rev. 3.0, 10/02, page 479 of 686