External Address Space Access Timing; Figure 6.7 Pin States During On-Chip Peripheral Module Access - Hitachi H8S/2215 Series Hardware Manual

Figure 6.7 Pin States during On-Chip Peripheral Module Access

6.5.3

External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6.6.3, Basic Timing.
Rev. 3.0, 10/02, page 116 of 686
Address bus
,
Data bus
Bus cycle
T1
T2
Unchanged
High
High
High
High-impedance state