Normal Mode; Table 7.6 Register Functions In Normal Mode - Hitachi H8S/2215 Series Hardware Manual

7.4.5

Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA
to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single
transfer request, and this is executed the number of times specified in ETCRA. The transfer source
is specified by MARA, and the transfer destination by MARB. Table 7.6 summarizes register
functions in normal mode.
Table 7.6 Register Functions in Normal Mode
Register
23
MARA
23
MARB
15
ETCRB
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a
transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Rev. 3.0, 10/02, page 172 of 686
Function
0
Source address
register
0
Destination address
register
0
Transfer counter
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Number of transfers Decremented every
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
transfer; transfer ends
when count reaches
H'0000