Hitachi H8S/2215 Series Hardware Manual page 39

Hitachi single-chip microcomputer
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15.3.14 USB Endpoint Data Register 1i (UEDR1i).......................................................... 458
15.3.15 USB Endpoint Data Register 2i (UEDR2i).......................................................... 458
15.3.16 USB Endpoint Data Register 2o (UEDR2o)........................................................ 458
15.3.17 USB Endpoint Data Register 3i (UEDR3i).......................................................... 459
15.3.18 USB Endpoint Data Register 3o (UEDR3o)........................................................ 459
15.3.19 USB Endpoint Data Register 4i (UEDR4i).......................................................... 459
15.3.20 USB Endpoint Data Register 4o (UEDR4o)........................................................ 460
15.3.21 USB Endpoint Data Register 5i (UEDR5i).......................................................... 460
15.3.22 USB Endpoint Receive Data Size Register 0o (UESZ0o) ................................... 460
15.3.23 USB Endpoint Receive Data Size Register 2o (UESZ2o) ................................... 461
15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o) ................................... 461
15.3.25 USB Endpoint Receive Data Size Register 4o (UESZ4o) ................................... 461
15.3.26 USB Interrupt Flag Register 0 (UIFR0)............................................................... 461
15.3.27 USB Interrupt Flag Register 1 (UIFR1)............................................................... 464
15.3.28 USB Interrupt Flag Register 2 (UIFR2)............................................................... 466
15.3.29 USB Interrupt Flag Register 3 (UIFR3)............................................................... 468
15.3.30 USB Interrupt Enable Register 0 (UIER0)........................................................... 470
15.3.31 USB Interrupt Enable Register 1 (UIER1)........................................................... 470
15.3.32 USB Interrupt Enable Register 2 (UIER2)........................................................... 471
15.3.33 USB Interrupt Enable Register 3 (UIER3)........................................................... 471
15.3.34 USB Interrupt Select Register 0 (UISR0) ............................................................ 472
15.3.35 USB Interrupt Select Register 1 (UISR1) ............................................................ 472
15.3.36 USB Interrupt Select Register 2 (UISR2) ............................................................ 473
15.3.37 USB Interrupt Select Register 3 (UISR3) ............................................................ 473
15.3.38 USB Data Status Register (UDSR) ...................................................................... 474
15.3.39 USB Configuration Value Register (UCVR) ....................................................... 475
15.3.40 USB Time Stamp Registers H, L (UTSRH, UTSRL).......................................... 476
15.3.41 USB Test Register 0 (UTSTR0) .......................................................................... 477
15.3.42 USB Test Register 1 (UTSTR1) .......................................................................... 479
15.3.44 Module Stop Control Register B (MSTPCRB).................................................... 481
15.4 Interrupt Sources............................................................................................................... 482
15.5 Communication Operation................................................................................................ 484
15.5.1 Initialization ......................................................................................................... 484
15.5.2 USB Cable Connection/Disconnection ................................................................ 485
15.5.3 Suspend and Resume Operations......................................................................... 489
15.5.4 Control Transfer................................................................................................... 492
15.5.5 Interrupt-In Transfer: (EP1i is specified as Endpoint) ......................................... 499
Rev. 3.0, 10/02, page xxxix of lviii

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