Hitachi H8S/2215 Series Hardware Manual page 541

Transfer
Register Bit Mode
UIFR2 2 Bulk_out transfer
(EP4o)
3 —
4 Interrupt_in transfer
(EP5i)
5
6 —
7 —

UIFR3 0
(Status)
1
2
3
4
5
6
7
Notes: *1 EP0 interrupts must be assigned to the same interrupt request signal.
*2 An EP2i DMA transfer request is specified by the EP2iT1 and EP2iT0 bits of UDMAR.
*3 An EP2o DMA transfer request is specified by the EP2oT1 and EP2oT0 bits of UDMAR.
*4 An EP4i DMA transfer request is specified by the EP4iT1 and EP4iT0 bits of UDMAR.
*5 An EP4oDMA transfer request is specified by the EP4oT1 and EP4oT0 bits of UDMAR.
*6 The suspend/resume interrupt request IRQ6 must be specified to be detected at the
falling edge (IRQ6SCB, A=01 in ISCRH) by the interrupt controller register.
• EXIRQ0 signal
The EXIRQ0 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ0 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
• EXIRQ1 signal
The EXIRQ1 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ1 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
• IRQ6 signal
The IRQ6 signal is specific to the suspend/resume interrupt request. The rising edge of the
IRQ6 signal is output at the transition from the suspend state or from the resume state.
Interrupt
Source Description
EP4oREADY EP4o data ready
Reserved —
EP5iTS EP5i transfer
completion
EP5iTR EP5i transfer request
Reserved —
Reserved —
VBUSi VBUS interrupt
VBUSs VBUS status
SPRSi Suspend/resume
interrupt
SPRSs Suspend/resume
status
SETI Set_Interface
detection
SETC Set_Configuration
detection
SOF Start of Frame packet
detection
CK48READY
USB bus clock
stabilization detection
Interrupt
Request DMAC
Signal Activation
EXIRQ0 or DREQ0 or
EXIRQ1 DREQ1*
— —
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
— X
— X
EXIRQ0 or
X
EXIRQ1
X X
IRQ6 *
6
X
X X
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
EXIRQ0 or
X
EXIRQ1
Rev. 3.0, 10/02, page 483 of 686
5