Hitachi H8S/2215 Series Hardware Manual page 11

Section
7.1 Features
Figure 7.1 Block Diagram
of DMAC
7.4.9 DMAC Bus Cycles
(Dual Address Mode)
9.1.4 Pin Functions
Table 9.8 P11 Pin
Function
Table 9.9 P10 Pin
Function
9.2.5 Pin Functions
Table 9.13 P33 Pin
Function
Table 9.16 P30 Pin
Function
9.8.3 Port C Register
(PORTC)
10.1 Features
Table 10.1 TPU
Functions
Page
Description
Figure amended
142
Internal interrupts
Note added
182,
184
Note: * TEND output cannot be used with this LSI.
Address amended
224
(Incorrect) Other than (B'1111)
(Correct) Other than (B'1110 to B'1111)
Address amended
(Incorrect) Other than (B'1111)
(Correct) Other than (B'1101 to B'1111)
Pin function amended
227
TE
P33DDR
Pin function
Pin function amended
228
TE
P30DDR
Pin function
Note added
244
Note: * Determined by the states of pins PC7 to PC0.
Channel 0 amended
265
Item
General registers/buffer
registers
TGI0A
TGI1A
TGI2A
TXI0
RXI0
TXI1
RXI1
ADI
Control logic
0
0
P33 input P33 output
0
0
P30 input P30 output
Channel 0 Channel 1
TGRC_0 not possible
TGRD_0
Rev. 3.0, 10/02, page xi of lviii
1
1
TxD1 output
1
1
TxD0 output
Channel 2
not possible