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5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
8.8
Usage Notes
8.8.1
Module Stop
When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the DTC enters the
module stop state. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating.
8.8.2
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
8.8.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are masked, multiple activation sources can be set at one time (only at the initial setting) by writing
data after executing a dummy read on the relevant register.
8.8.4
DMAC Transfer End Interrupt
When DTC transfer is activated by a DMAC transfer end interrupt, the DMAC's DTE bit is not
subject to DTC control, regardless of the transfer counter and DISEL bit, and the write data has
priority. Consequently, an interrupt request is not sent to the CPU when the DTC transfer counter
reaches 0.
Rev. 3.0, 10/02, page 216 of 686
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