Usb Trigger Register 1 (Utrg1) - Hitachi H8S/2215 Series Hardware Manual

Note: As triggers to EP3i and EP3o for Isochronous transfer are automatically generated each
time the SOF packet is received from the host, the user need not generate triggers to EP3i
and EP3o. Accordingly, data write to UEDR3i and data read from UEDR3o must be
completed before the next packet has been received.
15.3.6

USB Trigger Register 1 (UTRG1)

UTRG1 generates one-shot triggers to the FIFO for each endpoint EP4 and EP5.
Bit Bit Name Initial Value R/W
7–3 — 0
2 EP5iPKTE 0
1 EP4oRDFN 0
0 EP4iPKTE 0
Rev. 3.0, 10/02, page 452 of 686
Description
R Reserved
These bits are always read as 0 and cannot be
modified.
W EP5i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to the
EP5i IN FIFO.
W EP4o Read Completion
0: Performs no operation
1: Writes 1 to this bit after reading data for EP4o OUT
FIFO. EP4o FIFO has a dual FIFO
trigger is generated to the currently effective FIFO.
W EP4i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to the
EP4i IN FIFO. EP4i FIFO has a dual FIFO
configuration.
currently effective FIFO.
configuration.
This trigger is generated for the
This