Usb Trigger Register 0 (Utrg0) - Hitachi H8S/2215 Series Hardware Manual

15.3.5

USB Trigger Register 0 (UTRG0)

UTRG0 generates one-shot triggers to the FIFO for each endpoint EP0 to EP2.
Bit Bit Name Initial Value R/W
7 — 0
6 — 0
5 EP2oRDFN 0
4 EP2iPKTE 0
3 EP1iPKTE 0
2 EP0oRDFN 0
1 EP0iPKTE 0
0 EP0sRDFN 0
Description
R Reserved
R These bits are always read as 0 and cannot be
modified.
W EP2o Read Completion
0: Performs no operation
1: Writes 1 to this bit after reading data for EP2o OUT
FIFO. EP2o FIFO has a dual FIFO
trigger is generated to the currently effective FIFO.
W EP2i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to the
EP2i IN FIFO. EP2i FIFO has a dual FIFO
configuration. This trigger is generated for the currently
effective FIFO.
W EP1i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to the
EP1i IN FIFO.
W EP0o Read Completion
0: Performs no operation
1: Writes 1 to this bit after reading data for EP0o OUT
FIFO. This trigger enables the next packet to be
received.
W EP0i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to the
EP0i IN FIFO.
W EP0s Read Completion
0: Performs no operation. A NAK handshake is
returned in response to transmit/receive requests from
the host in the data stage until 1 is written to this bit.
1: Writes 1 to this bit after reading data for EP0s OUT
FIFO. After receiving the setup command, this trigger
enables the next packet to be received by the EP0i
and EP0o in the data stage. EP0s can always be
overwritten and receive data regardless of this trigger.
configuration.
Rev. 3.0, 10/02, page 451 of 686
This