Usage Notes; Dmac Register Access During Operation; Figure 7.27 Dmac Register Update Timing - Hitachi H8S/2215 Series Hardware Manual

7.6

Usage Notes

7.6.1

DMAC Register Access during Operation

Except for forced termination, the operating (including transfer waiting state) channel setting
should not be changed. The operating channel setting should only be changed when transfer is
disabled. Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(1) DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 7.27 shows an example of the update timing for DMAC registers in dual address
transfer mode.
φ
DMA Internal
address
Idle
DMA control
DMA register
[1]
operation
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
(2) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.28.
Rev. 3.0, 10/02, page 192 of 686
DMA transfer cycle
DMA read DMA write
Transfer
Transfer
destination
source
Read
Write
[2]

Figure 7.27 DMAC Register Update Timing

Transfer
source
Read
Idle
[1]
DMA last transfer cycle
DMA read
DMA write
Transfer
destination
Write Dead
[2'] [3]
DMA
dead
Idle