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TE bit
SCK output pin
TxD output pin
Port input/output
Port
Figure 13.28 Port Pin State of Asynchronous Transmission Using Internal Clock
TE bit
SCK output pin
TxD output pin Port input/output
Port
Note: * Initialized by the software standby.
Figure 13.29 Port Pin State of Synchronous Transmission Using Internal Clock
• Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode,
software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR,
and SSR are reset. If a transition is made without stopping operation, the data being received
will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
Figure 13.30 shows a sample flowchart for mode transition during reception.
Rev. 3.0, 10/02, page 412 of 686
Start of transmission
High output
Start
SCI TxD output
Start of transmission
High output
SCI TxD output
Transition
End of
to software
transmission
standby
Stop
Transition
End of
to software
transmission
standby
Final TxD
Port input/output
bit retention
Exit from
software
standby
Port input/output
Port input/output
High output
SCI TxD
Port
output
Exit from
software
standby
Port input/output
High output*
SCI TxD
Port
output
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