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15.6
DMA Transfer Specifications
15.6.1
Overview
This module incorporates the interface that supports dual-address transfer by means of the on-chip
DMAC. Endpoints that can be transferred by the on-chip DMAC are EP2 and EP4 in Bulk transfer
(corresponding registers are UEDR2i, UEDR2o, UEDR4i, and UEDR4o). In DMA transfer, the
USB module must be accessed as an external device in area 6. The USB module cannot be
accessed as a device with external ACK (single-address transfer cannot be performed.). 0-byte data
transfer to EP2o or EP4o is ignored even if the DMA transfer is enabled by setting the EP2oT1 or
EP4oT1 bit of UDMAR to 1.
15.6.2
On-Chip DMAC Settings
The on-chip DMAC must be specified as follows: A USB request (DREQ signal), activated by
low-level input, byte size, full-address mode transfer, and the DTA bit of DMABCR =1. After
completing the DMA transfers of specified time, the DMAC automatically stops. Note, however,
that the USB module keeps the DREQ signal low while data to be transferred by the on-chip
DMAC remains regardless of the DMAC status.
15.6.3
EP2i and EP4i DMA Transfer
The EP2iT1 and EP4iT1 bits of UDMAR enable DMA transfer. The EP2iT0 and EP4iT0 bits of
the UDMAR specify the DREQ signal to be used by the DMA transfer. When the EP2iT1 or
EP4iT1 is set to 1, the DREQ signal is driven low if at least one of EP2i and EP4i data FIFOs are
empty; the DREQ signal is driven high if both EP2i and EP4i data FIFOs are full.
15.6.4
EP2o and EP4o DMA Transfer
The EP2oT1 and EP4oT1 bits of UDMAR enable DMA transfer. The EP2oT0 and EP4oT0 bits of
the UDMAR specify the DREQ signal to be used by the DMA transfer. When the EP2oT1 or
EP4oT1 is set to 1, the DREQ signal is driven low if at least one of EP2o and EP4o data FIFOs are
full (ready state); the DREQ signal is driven high if both EP2o and EP4o data FIFOs are empty
when all receive data items are read.
Rev. 3.0, 10/02, page 513 of 686
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