Item
SCI
Input
clock
cycle
Input clock pulse
width
Input clock rise time
Input clock fall time
Transmit data delay
time
Receive data setup
time (synchronous)
Receive data hold
time (synchronous)
A/D
Trigger input setup
converter
time
Boundary
TCK cycle time
scan
TCK high level pulse
width
TCK low level pulse
width
TRST pulse width
TRST setup time
TDI setup time
TDI hold time
TMS setup time
TMS hold time
TDO delay time
Symbol
Asynchro-
t
Scyc
nous
Synchro-
nous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
t
cyc
t
TCKH
t
TCKL
t
TRSW
t
TRSS
t
TDIS
t
TDIH
t
TMSS
t
TMSH
t
TDOD
Min
Max
4
—
6
—
0.4
0.6
—
1.5
—
1.5
—
60
60
—
60
—
40
—
62.5
0.6
0.4
0.6
0.4
—
20
250
—
30
—
10
—
30
—
10
—
—
40
Rev. 3.0, 10/02, page 665 of 686
Unit
Test Conditions
t
Figure 24.18
cyc
t
Scyc
t
cyc
ns
Figure 24.19
ns
Figure 24.20
ns
Figure 24.21
t
cyc
t
cyc
t
Figure 24.22
cyc
ns
ns
Figure 24.23