Hitachi H8S/2215 Series Hardware Manual page 51

Hitachi single-chip microcomputer
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Section 19 Flash Memory (F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory........................................................................... 558
Figure 19.2 Flash Memory State Transitions.............................................................................. 559
Figure 19.3 Boot Mode............................................................................................................... 561
Figure 19.4 User Program Mode ................................................................................................ 562
Figure 19.5 Flash Memory Block Configuration........................................................................ 563
Figure 19.6 SCI System Configuration in Boot Mode ............................................................... 572
Figure 19.9 Flowchart for Flash Memory Emulation in RAM ................................................... 581
Figure 19.10 Example of RAM Overlap Operation...................................................................... 582
Figure 19.11 Program/Program-Verify Flowchart ....................................................................... 584
Figure 19.12 Erase/Erase-Verify Flowchart ................................................................................. 586
Figure 19.13 Memory Map in Programmer Mode........................................................................ 588
Section 20 Masked ROM
Figure 20.1 Block Diagram of On-Chip Masked ROM (256 kbytes)........................................ 593
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................... 595
Figure 21.2 Connection of Crystal Resonator (Example)........................................................... 599
Figure 21.3 Crystal Resonator Equivalent Circuit...................................................................... 599
Figure 21.4 External Clock Input (Examples) ............................................................................ 600
Figure 21.5 External Clock Input Timing................................................................................... 601
Figure 21.6 Connection of Ceramic Resonator........................................................................... 602
Figure 21.7 Connection of Ceramic Resonator........................................................................... 602
Figure 21.8 48-MHz External Clock Input Timing .................................................................... 603
Figure 21.9 Pin Handling when 48-MHz External Clock is Not Used ....................................... 603
Figure 21.10 Example of PLL Circuit .......................................................................................... 604
Figure 21.11 Note on Board Design of Oscillator Circuit ............................................................ 605
Figure 21.12 Example of External Clock Switching Circuit ........................................................ 605
Figure 21.13 Example of External Clock Switchover Timing...................................................... 606
Section 22 Power-Down Modes
Figure 22.1 Mode Transition Diagram ....................................................................................... 609
Figure 22.2 Medium-Speed Mode Transition and Clearance Timing ........................................ 614
Figure 22.3 Software Standby Mode Application Example ....................................................... 618
Figure 22.4 Hardware Standby Mode Timing (Example) .......................................................... 619
Figure 22.5 Timing of Transition to Hardware Standby Mode .................................................. 619
Figure 22.6 Timing of Recovery from Hardware Standby Mode............................................... 620
Section 24 Electrical Characteristics
Figure 24.1 Power Supply Voltage and Operating Ranges ........................................................ 650
Figure 24.2 Output Load Circuit ................................................................................................ 654
Figure 24.3 System Clock Timing.............................................................................................. 655
Rev. 3.0, 10/02, page li of lviii

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