Hitachi H8S/2215 Series Hardware Manual page 389

11.3.4 Time Control Registers (TCR)
The TCR registers select the clock source and the time at which TCNT is cleared, and enable
interrupts.
Bit Bit Name Initial Value
7 CMIEB 0
6 CMIEA 0
5 OVIE 0
4 CCLR1 0
3 CCLR0 0
2 CKS2 0
1 CKS1 0
0 CKS0 0
R/W Description
R/W Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests (CMIB) are
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
R/W Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
R/W Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
R/W Counter Clear 1 and 0
R/W
These bits select the method by which TCNT is
cleared
00: Clear is disabled
01: Clear by compare match A
10: Clear by compare match B
11: Clear by rising edge of external reset input
R/W Clock Select 2 to 0
R/W
These bits select the clock input to TCNT and count
R/W
condition. See table 11.2.
Rev. 3.0, 10/02, page 331 of 686