Gpt Pwm Configuration Register (Gpwmn) - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
31–16 PRE
15–0 CNT
11.3.3

GPT PWM Configuration Register (GPWMn)

31 30 29
R
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Reg MBAR + 0x808 (GPWM0), 0x818 (GPWM1), 0x828 (GPWM2), 0x838 (GPWM3)
Addr
Bits Name
31–16 WIDTH
15–9 —
8 PWMOP
11-6
Table 11-3. GCIRn Field Descriptions
Prescaler. Prescale amount applied to internal counter (in clocks).
Note that in addition to other enable bits and field settings, the PRE field must be written as
non-zero to enable counter operation for all modes except the simple GPIO mode. A prescale of
0x0001 means one clock per count increment.
Count value. Sets number of prescaled counts applied to reference events, as follows:
IC—Field has no effect, internal counter starts at 0.
OC—Number of prescaled counts counted before creating output event.
PWM—Number of prescaled counts defining the PWM output period.
Internal Timer—Number of prescaled counts counted before timer (or watchdog) expires.
Reading this register only returns the programmed value, intermediate values of the internal
counter are not available to software.
28 27 26
0 0 0
12 11 10
0 0 0
0 0 0
Figure 11-3. GPT PWM Configuration Register (GPWMn)
Table 11-4. GPWMn Field Descriptions
PWM width. Used in PWM mode only. Defines ON time for output in prescaled counts. Similar to
count value, which defines the period. ON time overlays the period time.
If WIDTH = 0, output is always OFF.
If WIDTH exceeds count value, output is always ON.
ON and OFF polarity is set by the PWMOP bit.
Reserved. Should be cleared.
PWM output polarity. Defines PWM output polarity for OFF time. Opposite state is ON time. PWM
cycles begin with ON time.
0 PWM output is low during OFF time
1 PWM output is high during OFF time
MCF548x Reference Manual, Rev. 3
Description
25 24 23 22
WIDTH
0 0 0 0
9 8 7 6
0 PWM 0 0
OP
0 0 0 0
Description
21 20 19 18
0 0 0 0
5 4 3 2
0 0 0 0
0 0 0 0
Freescale Semiconductor
17 16
0 0
1 0
0 LOAD
0 0