Interrupt Vector Offset Registers (Ivors) - Freescale Semiconductor e200z3 Reference Manual

Register Model
32
Field
Reset
R/W
SPR
IVPR fields are defined in
Bits Name
32–47 Vector Defines the base location of the vector table, aligned to a 64-Kbyte boundary. Provides the high-order 16
bits of the location of all interrupt handlers. IVPR || IVOR n values are concatenated to form the address of
Base
the handler in memory.
48–63 — Reserved, should be cleared.
2.8.1.7

Interrupt Vector Offset Registers (IVORs)

IVORs, shown in Figure
each interrupt type.
32
Field
Reset
R/W
SPR
The IVOR fields are defined in
Bits Name
32–47 — Reserved, should be cleared.
48–59 Vector offset Provides a quad-word index from the base address provided by the IVPR to locate an interrupt handler.
60 — Reserved, should be cleared.
61–63 CS Context selector (e200z3-specific). When multiple hardware contexts are supported, this field is used
to select an operating context for the interrupt handler. This value is loaded into the CURCTX field of
the context control register (CTXCR) as part of the interrupt vectoring process. When multiple hardware
contexts are not supported, CS is not implemented and is read as zero.
2-22
Vector Base
Undefined on m_por assertion, unchanged on p_reset_b assertion
Figure 2-16. Interrupt Vector Prefix Register (IVPR)
Table 2-10.
Table 2-10. IVPR Field Descriptions
2-17, hold the quad-word index from the base address provided by the IVPR for
—
Undefined on m_por assertion, unchanged on p_reset_b assertion
(See
Figure 2-17. Interrupt Vector Offset Registers (IVOR)
Table 2-11.
Table 2-11. IVOR Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
47 48
R/W
SPR 63
Description
47 48
Vector offset
R/W
Table 2-12.)
Setting Description
63
—
59 60 61 63
— CS
Freescale Semiconductor