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7.3.2
Interrupt Control Register Functions
The interrupt control registers (ICR00 to ICR15) consist of the following four functional
bits:
• Interrupt level setting bits (IL2 to IL0)
• Extended intelligent I/O service (EI
• Extended intelligent I/O service (EI
• Extended intelligent I/O service (EI
■ Configuration of Interrupt Control Registers (ICR)
Figure 7.3-3 shows the configuration of the interrupt control register (ICR) bits.
Figure 7.3-3 Configuration of Interrupt Control Registers (ICR)
Writing to interrupt control register (ICR)
Reading of interrupt control register (ICR)
R:
W:
- :
References:
• The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI
activated. To activate EI
When EI
• ICS1 and ICS0 are valid only for writing. S1 and S0 are valid only for reading.
■ Interrupt Control Register Functions
●
Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt level of the corresponding peripheral function. These bits are initialized to level
7 (no interrupt) by a reset.
Table 7.3-2 shows the correspondence between the interrupt level setting bits and interrupt levels.
Address
0000B0
H
to
0000BF
H
Address
0000B0
H
to
0000BF
H
Read-only
Write-only
Not used
2
OS, set the ISE bit to "1". To not activate EI
2
OS is not activated, setting ICS3 to ICS0 is optional.
2
OS) enable bit (ISE)
2
OS) channel selection bits (ICS3 to ICS0)
2
OS) status (S1 and S0)
CHAPTER 7 INTERRUPT
Initial value
Initial value
2
OS) has been
2
OS, set the ISE bit to "0".
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