Interrupt Control Register (Icr) - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.10.2 Interrupt Control Register (ICR)

The interrupt control register (ICR: Interrupt Control Register), located in the interrupt
controller, sets the level of an interrupt request. An ICR is provided for each of the
interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the
CPU through a bus.
■ Configuration of Interrupt Control Register (ICR)
Figure 3.10-1 shows the configuration of the interrupt control register (ICR) bits.
Figure 3.10-1 Configuration of Interrupt Control Register Bit
Address bit
000440 to
H
00046F
H
The following describes the functions of the interrupt control register (ICR) bits.
[bit4] ICR4
This bit is always set to "1".
[bit3 to bit0] ICR3 to ICR0
These bits are the low-order 4 bits of the interrupt level of the corresponding interrupt source.
They can be read and written to.
Together with bit4, a value between 16 and 31 can be set in the ICR.
■ Mapping of Interrupt Control Register (ICR)
Table 3.10-3 shows the relationship between interrupt sources, interrupt control register, and
interrupt vectors.
Table 3.10-3 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors
Interrupt
source
IRQ00
IRQ01
IRQ02
...
...
IRQ45
IRQ46
IRQ47
TBR initial value: 00F FC00
Note: See "CHAPTER 11 INTERRUPT CONTROLLER".
82
7 6 5 4
- - - ICR4
R
Interrupt control register
ICR00 00000440
ICR01 00000441
ICR02 00000442
...
...
ICR45 0000046D
ICR46 0000046E
ICR47 0000046F
H
3 2 1
ICR3 ICR2 ICR1
R/W R/W R/W
Corresponding interrupt vector
Number
Hexadecimal
10
H H
11
H H
12
H H
... ...
... ...
3D
H H
3E
H H
3F
H H
0 [Initial value]
---111111
ICR0
B
R/W
Address
Decimal
16 TBR + 3BC
17 TBR + 3B8
18 TBR + 3B4
... ...
... ...
61 TBR + 308
62 TBR + 304
63 TBR + 300
H
H
H
H
H
H