Serial Input Data Register 0 To 3(Sidr0 To Sidr3) And Serial Output Data Register0 To 3(Sodr0 To Sodr3) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART
21.4.4 Serial Input Data Register 0 to 3(SIDR0 to SIDR3) and
Serial Output Data Register0 to 3(SODR0 to SODR3)
Serial input data and serial output data registers are located in the same address. They
function as a serial input data register in reading, while in writing as a serial output data
register.
Serial Input Data Register 0 to 3 (SIDR0 to SIDR3)
Figure 21.4-5 shows the bit configuration of the serial input data register.
Figure 21.4-5 Serial Input Data Register 0 to 3 (SIDR0 to SIDR3)
R : Read only
X : Indeterminate
Serial input data register 0 to 3 (SIDR0 to SIDR3) is a data buffer register for receiving serial data.
• The serial data signals sent to the serial input pins (SIDR0 to SIDR3) are converted in the shift register,
and stored in the serial input data registers 0 to 3 (SIDR0 to SIDR3).
• When the data length is 7 bits, the upper one bit (SIDR0 to SIDR3:D7) becomes invalid.
• When the receiving data is stored in the serial input data registers 0 to 3 (SIDR0 to SIDR3), the receiving
data full flag bit (SSR0 to SSR3: RDRF) is set to "1". When receiving interrupts are enabled (SSR0 to
SSR3: RIE=1), receiving interrupt requests are generated.
• Read the serial input data registers 0 to 3 (SIDR0 to SIDR3) in the state that the receiving data full flag
bit (SSR0 to SSR3: RDRF) is set to "1". When the receiving data full flag bit (SSR0 to SSR3: RDRF)
reads the serial input data registers 0 to 3 (SIDR0 to SIDR3), it is automatically cleared to "0".
• If any receiving error occurs (SSR0 to SSR3: PE, ORE, or FRE is "1"), the data of the serial input data
registers 0 to 3 (SIDR0 to SIDR3) is invalid.
490
Address bit6
bit7
ch0 : 000022
H
D7
ch1 : 000028
H
ch2 : 00002E
H
R
ch3 : 000034
H
bit5 bit2
bit4 bit3
D6 D5 D4 D3 D2
R
R R R
bit1 bit0
Initial value
XXXXXXXX
D1 D0
R R
R
B