Serial Input Data Register (Sidr)/Serial Output Data Register (Sodr) - Fujitsu FR60 Hardware Manual

CHAPTER 13 UART
13.2.3 Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)
These registers are data buffer registers for receiving and sending.

■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

Figure 13.2-5 shows the bit configurations of the serial input data register (SIDR) and the serial
output data register (SODR).
Figure 13.2-5 Bit Configurations of the Serial Input Data Register (SIDR) and the Serial Output Data
SIDR
Address: 000061
H
000069
H
000071
H
SODR
Address: 000061
H
000069
H
000071
H
If the data length is 7 bits, bit7 (D7) of SIDR and SODR is invalid data. Write to the SODR
register only while the TDRE bit of the SSR register is set to "1".
Note:
Writing to the register with this address means writing to the SODR register. Reading from the
register with this address means reading from the SIDR register.
368
Register (SODR)
bit 7 6 5
(ch.0)
D7 D6 D5
(ch.1)
R R R
(ch.2)
bit 7 6 5
(ch.0)
D7 D6 D5
(ch.1)
W W W
(ch.2)
4 3 2 1
D4 D3 D2 D1
R R R R
4 3 2 1
D4 D3 D2 D1
W W W W
0 Initial value
XXXXXXXX
D0
B
R
0 Initial value
XXXXXXXX
D0
B
W