Input Capture - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 10 16-BIT I/O TIMER

10.3.3 Input Capture

The input capture has the following two registers:
• Input capture data register (IPCO0 to IPCO3)
• Control status register (ICS23 and ICS01)
■ Input Capture Data Register (IPCO0 to IPCO3)
Input capture data registers (IPCO0 to IPCO3) are used to retain 16-bit free-run timer values
when a valid edge of the corresponding external pin input waveform is detected.
Figure 10.3-6 Input Capture Data Registers (IPCO0 to IPCO3)
High-order byte of
the input capture data register
Address:
ch.0 000063
ch.1 000065
ch.2 000067
ch.3 000069
Read/write
Initial value
Low-order byte of
the input capture data register
Address:
ch.0 000062
ch.1 000064
ch.2 000066
ch.3 000068
Read/write
Initial value
Note:
This register requires word access. No writing is possible.
■ Control Status Registers (ICS23 and ICS01)
High-order byte of
the control status register
Address:
00006B
Read/write
Initial value
Low-order byte of
the control status register
Address:
00006A
Read/write
Initial value
Note:
This register requires byte access.
172
15 14
bit
H
H
H
CP15 CP14 CP13
H
(R) (R) (R)
(X) (X) (X)
7 6
bit
H
H
CP07 CP06 CP05
H
H
(R) (R) (R)
(X) (X) (X)
Figure 10.3-7 Control Status Registers (ICS23 and ICS01)
15 14
bit
ICP3 ICP2
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0)
7 6
bit
ICP1 ICP0
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0)
13 12 11
CP12 CP11 CP10
(R) (R) (R)
(X) (X) (X)
5 4
3
CP04 CP03 CP02
(R) (R) (R)
(X) (X) (X)
13 12 11 10
ICE3 ICE2 EG31 EG30 EG21 EG20
(0) (0) (0) (0)
5 4 3
ICE1 ICE0 EG11 EG10 EG01 EG00
(0) (0) (0)
10 9
8
IPCO0/1/2/3
CP09 CP08
(R) (R)
(X) (X)
2 1 0
IPCO0/1/2/3
CP01 CP00
(R) (R)
(X) (X)
9 8
(0) (0)
2 1 0
(0) (0) (0)
ICS23
ICS01