Pin States During Reset - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.5.3

Pin States During Reset

A reset initializes the pin state.
Pin States during Reset
When a reset source is generated, all I/O pins (peripheral pins), with some exceptions, go to the
high-impedance state and the mode data is read from internal ROM (pins with a pull-up resistor
(optional) go to the "H" level).
Pin States after Reading Mode Data
The I/O pins except for some pins remain in the high-impedance state immediately after reading
the mode data. (Pins with a pull-up resistor (optional) go to the "H" level.)
Check:
For devices connected to pins that change to high-impedance state when a reset source
occurs, take care that malfunction does not occur due to the change in the pin states.
Reference:
See Appendix E, "MB89120/120A Series Pin States" for pin states at times other than a
reset.
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