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CHAPTER 3 CPU
3.6.5
State of Each Pin at Reset
This section explains the state of each pin at reset.
I State of Pins at Reset
The state of the pins during reset operation is determined by the settings of the mode pins (MD2 to MD0).
G
When internal vector mode set:
• If the internal vector mode is set, all I/O pins enter the high-impedance state and mode data is read to
internal ROM.
I State of Pins after Mode Data Read
• The I/O pins are all set to the high-impedance state, and the mode data read destination is the internal
ROM.
Note:
Be careful not to let those devices malfunction which are connected to pins that enter the high
impedance state when a reset trigger event occurs.
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