Debug Mcu Configuration Register - ST STM32F205 series Reference Manual

RM0033
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
•
In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by
the debugger. This will feed HCLK with the same clock that is provided to FCLK
(system clock previously configured by the software).
•
In Stop mode, the bit DBG_STOP must be previously set by the debugger. This will
enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.
32.16.2 Debug support for timers, watchdog, bxCAN and I
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
•
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
•
They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.
2
For the I
For timers having complementary outputs, when the counter is stopped
(DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset) for safety
purposes.
32.16.3

Debug MCU configuration register

This register allows the configuration of the MCU under DEBUG. This concerns:
•
Low-power mode support
•
Timer and watchdog counter support
•
bxCAN communication support
• Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR register
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
C, the user can choose to block the SMBUS timeout during a breakpoint.
RM0033 Rev 8
Debug support (DBG)
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C
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