Debug Mcu Configuration Register - ST STM32F100 Series Reference Manual

RM0041
For timers having complementary outputs, when the counter is stopped
(DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset) for safety
purposes.
25.15.3

Debug MCU configuration register

This register allows the configuration of the MCU under DEBUG. This concerns:
•
Low-power mode support
•
Timer and watchdog counter support
•
Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR register
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29
Reserved
15 14 13
DBG_I2C1 DBG_
_SMBUS_ TIM4_ TIM3_
Res.
TIMEOUT STOP
rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:25 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x = 12..14)
Bits 24:22 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x = 17..15)
Bit 21
28 27 26 25
DBG_ DBG_
DBG_
TIM14 TIM13
TIM12_
_STO _STO
STOP
P P
rw rw rw
12 11 10 9
DBG_
DBG_ DBG_ DBG_
WWDG
TIM2_ TIM1_
_
STOP STOP STOP
STOP
rw rw rw rw
0: The clock of the involved timer counter is fed even if the core is halted
1: The clock of the involved timer counter is stopped when the core is halted
0: The clock of the involved timer counter is fed even if the core is halted
1: The clock of the involved timer counter is stopped when the core is halted
Reserved, must be kept at reset value.
24 23 22 21
DBG_ DBG_ DBG_
TIM17 TIM16 TIM15
_STO _STO _STO
Res.
P P P
rw rw rw
8 7 6 5
DBG_ TRACE_ TRACE
IWDG MODE _
STOP [1:0] IOEN
rw rw rw rw
RM0041 Rev 6
Debug support (DBG)
20 19 18 17
DBG_ DBG_ DBG_
TIM7_ TIM6_ TIM5_
Res.
STOP STOP STOP
rw rw rw
4 3 2
DBG_
DBG_
STAND
STOP
Reserved
BY
rw rw
16
DBG_I2C2
_SMBUS_
TIMEOUT
rw
1 0
DBG_
SLEEP
rw
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