Smartcard; Figure 258. Iso 7816-3 Asynchronous Protocol - ST STM32F100 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
As soon as HDSEL is written to 1:
•
the TX and RX lines are internally connected
•
the RX pin is no longer used
•
the TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as floating input (or output high open-drain) when not driven by the USART.
Apart from this, the communications are similar to what is done in normal USART mode.
The conflicts on the line must be managed by the software (by the use of a centralized
arbiter, for instance). In particular, the transmission is never blocked by hardware and
continue to occur as soon as a data is written in the data register while the TE bit is set.
23.3.11

Smartcard

The Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
smartcard mode, the following bits must be kept cleared:
•
LINEN bit in the USART_CR2 register,
•
HDSEL and IREN bits in the USART_CR3 register.
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard. The USART should be configured as:
• 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
•
1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2
register.
Note: It is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop
bits for both transmitting and receiving to avoid switching between the two configurations.
Figure 258
error.
When connected to a Smartcard, the TX output of the USART drives a bidirectional line that
is also driven by the Smartcard. The TX pin must be configured as open-drain.
Smartcard is a single wire half duplex communication protocol.
•
Transmission of data from the transmit shift register is guaranteed to be delayed by a
minimum of 1/2 baud clock. In normal operation a full transmit shift register starts
626/709
shows examples of what can be seen on the data line with and without parity

Figure 258. ISO 7816-3 asynchronous protocol

Without Parity error
S 0 1
Start bit
WithParity error
S 0
Start bit
RM0041 Rev 6
2 3 4 5 6 7
1 2 3 4 5 6 7
Guard time
p
Guard time
p
Line pulled low by receiver
during stop in case of parity error
RM0041
MSv31162V1