Rising Trigger Selection Register (Exti_Rtsr); Falling Trigger Selection Register (Exti_Ftsr) - ST STM32F207 Series Reference Manual

RM0033
8.3.3

Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:23
Bits 22:0 TRx: Rising trigger event configuration bit of line x
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
8.3.4

Falling trigger selection register (EXTI_FTSR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:23
Bits 22:0 TRx: Falling trigger event configuration bit of line x
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,
the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
28 27 26 25
Reserved
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
Reserved, must be kept at reset value (0).
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
28 27 26 25
Reserved
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
Reserved, must be kept at reset value (0).
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
24 23 22
TR22 TR21
rw
8 7 6
TR8 TR7 TR6
rw rw rw
24 23 22
TR22 TR21
rw
8 7 6
TR8 TR7 TR6
rw rw rw
RM0033 Rev 9
Interrupts and events
21 20 19 18
TR20 TR19 TR18
rw rw rw rw
5 4 3 2
TR5 TR4 TR3 TR2
rw rw rw rw
21 20 19 18
TR20 TR19 TR18
rw rw rw rw
5 4 3 2
TR5 TR4 TR3 TR2
rw rw rw rw
17 16
TR17 TR16
rw rw
1 0
TR1 TR0
rw rw
17 16
TR17 TR16
rw rw
1 0
TR1 TR0
rw rw
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