I 2 C Interface; I 2 C Interfaces Signals; Interface Routing Guidelines; Table 6. I 2 C Interface Signals - Intel Quark SE Series Platform Manual

I2C Interface
4.0 I 2 C Interface
I 2 C is a two-wire serial bus for inter-IC communication. One wire is for data, and the
other wire is for clock. The Intel® Quark™ SE microcontroller C1000 has two I
controllers, each with its own independent two-wire bus.
4.1 I 2 C Interfaces Signals
Signals for the I
Table 6. I 2 C Interface Signals
Signal Name
I2C_M_x_CLK
I2C_M_x_DATA
The following is a list of the I

Two I
 Support for both master and slave operation
 Operational speeds:



 7-bit or 10-bit addressing
 Support for clock stretching by slave devices
 Multi-master arbitration
 Spike suppression
 Hardware handshake interface to support DMA capability
 Interrupt control

FIFO support with 16B deep RX and TX FIFOs
4.2

Interface Routing Guidelines

I 2 C clock and data signals require pull-up resistors. The pull-up size is dependent
on the bus capacitive load (this includes all device leakage currents).
June 2017
Document Number: 334715-004EN
2 C interfaces are illustrated in the table below.
Direction/ Type
I/O
I/O
2 C features:
2 C interfaces
Standard mode (0 to 100Kbps)
Fast mode (≤ 400Kbps)
Fast mode plus (≤ 1Mbps)
Description
I 2 C Serial Clock
I 2 C Serial Data
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
2 C
25