Pipeline Registers For Fixed-Point Arithmetic - Intel Agilex User Manual

Figure 8. Data Input Registers in Fixed-Point Arithmetic 27 x 27 Mode
Related Information
Configurations for Input, Pipeline, and Output Registers
Provides information about restrictions on fixed-point arithmetic input registers.

2.1.2. Pipeline Registers for Fixed-Point Arithmetic

In addition to the input and output registers, there are 2 columns of pipeline registers
for fixed-point arithmetic. Pipeline registers are used to get the maximum Fmax
performance. The pipeline registers can be bypassed if high Fmax is not needed.
The following variable precision DSP block signals control the pipeline registers within
the variable precision DSP block:
• CLK
• ENA[2..0]
• CLR[1]
Related Information
Configurations for Input, Pipeline, and Output Registers
Provides information about restrictions on fixed-point arithmetic pipeline registers.
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Intel Agilex Variable Precision DSP Blocks User Guide
16
2. Intel Agilex Variable Precision DSP Blocks Architecture
scanin[26..0]
ay[26..0]
az[25..0]
ax[26..0]
UG-20213 | 2019.04.02
CLK
ENA[2..0]
CLR[0]
scanout[26..0]
on page 62
on page 62
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