Pll Architecture; Pll Control Signals - Intel Agilex User Manual

2. Intel Agilex Clocking and PLL Architecture and Features
UG-20216 | 2019.04.02

2.2.4. PLL Architecture

Figure 8. I/O Bank I/O PLL High-Level Block Diagram for Intel Agilex Devices
Dedicated clock inputs
from the same I/O bank
Programmable clock routing
cascade input from I/O PLL
in the same I/O column
or dedicated clock Inputs
from other I/O bank in the
same I/O column
Figure 9. Fabric-Feeding I/O PLL High-Level Block Diagram for Intel Agilex Devices
Dedicated clock inputs
from the same I/O bank
Dedicated clock inputs from the
same I/O banks, or inputs from
other I/O banks in the same
I/O column or PLLs routed
over the global clock network

2.2.5. PLL Control Signals

You can use the reset signal to control PLL operation and resynchronization, and use
the locked signal to observe the status of the PLL.
2.2.5.1. Reset
The reset signal port of the IP core for I/O PLL is
The reset signal is the reset or resynchronization input for each I/O PLL. The device
input pins or internal logic can drive these input signals.
When the reset signal is driven high, the I/O PLL counters reset, clearing the I/O PLL
output and placing the I/O PLL out-of-lock. The VCO is then set back to its nominal
setting. When the reset signal is driven low again, the I/O PLL resynchronizes to its
input clock source as it re-locks.
Send Feedback
For single-ended clock inputs, only the CLKp and CLKn pins
have dedicated connection to the PLL.
4
inclk0
÷N
Clock
extswitch
Switchover
inclk1
clkbad0
Block
clkbad1
activeclock
You can choose non-dedicated feedback path option
for these compensation modes.
For single-ended clock inputs, only the CLKp and CLKn pins
have dedicated connection to the PLL.
4
inclk0
÷N
Clock
extswitch
Switchover
inclk1
clkbad0
Block
clkbad1
activeclock
You can choose non-dedicated feedback path option
for these compensation modes.
To DPA Block
Lock
locked
÷C0
Circuit
8
÷C1
÷C2
PFD CP LF VCO
8
÷C3
÷C6
÷M
Direct Compensation Mode
Zero Delay Buffer, External Feedback Modes
LVDS Compensation Mode
Source Synchronous, Normal Modes
Lock
locked
Circuit
÷C0
PFD CP LF VCO ÷C1
8
÷C2
÷M
Direct Compensation Mode
Zero Delay Buffer, External Feedback Modes
Source Synchronous, Normal Modes
.
reset
® ™
Intel Agilex
Cascade Output to
Adjacent I/O PLL
Programmable clock routing
LVDS RX/TX Clock
LVDS RX/TX Load Enable
External Memory Interface DLL
FBOUT This FBOUT port is fed by
the M counter in the PLLs.
FBIN
LVDS Clock Network
Programmable Clock Routing
Programmable clock routing
FBOUT This FBOUT port is fed by
the M counter in the PLLs.
FBIN
Programmable Clock Routing
Clocking and PLL User Guide
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